Help me for a motivation letter for a graduated student award

Dear Sir or Madam


I first would like to thank you for considering my request for the E-MRS Graduate Student Award. I have a strong motivation to be admitted.

I graduated in July 1999 from Zhejiang University in china with a degree in Material science and engineering. During my studies at the university, I had the opportunity to study in a course devoted to crystal science and semiconductor materials. It greatly influenced my deepest interest to semiconductor research domain. My final year undergraduate project concerns technology of optical-magnetic devices.

After graduation, in September of 2000, I joined IEMN research laboratory to be a graduate student. My first task involved the simulation and design of a new transistor HEMT on substrate InP. It was a challenge because both the physic of this transistor and the simulator were new for me. I successfully simulated the characteristics of a new 50 nm-gate HEMT on substrate InP without buffer layer. We used an isolation material (Si3N4) to tack place of the buffer layer and reduced thus the short channel effect.

During my term as a PhD student, my main research interest lied in Optimization of LDMOS on SOI in the 4th generation Advanced Bipolar CMOS-DMOS technology (ABCD-4). This technology is based on a remarkable patented process of Philips Semiconductor, which enhances SOI, allowing power components to be integrated easily alongside low-voltage analogue or digital circuitry on a single-chip. It is designed for applications from 12 V to 60 V. SOI's extreme versatility combined with its high packing density, very high power output, minimal power dissipation and simplified design-in make it an attractive commercial option, cutting the costs of products based on this process. The use of SOI leads to numerous advantages such as less waste heat, giving DMOS transistors excellent power handling capabilities, and enable the creation of real smart power circuits and ensuring excellent insulation and, as a result, a significant reduction in parasitic capacitances, leading to quicker and easier design-in.

Our aim is to optimise the parameters of the LDMOS in this technology such as drift region doping, SOI thickness, buried oxide thickness, etc so that to get better trade-off of the breakdown voltage and resistance on.

Since the channel of LDMOS is usually formed by a purely vertical implantation and a Large-Angle Tilt Implantation called LATID (usually 45 °), at the beginning of the research work, an accurate modelling of channelling was developed and the code was implemented in the simulator IMPACT. This study was published in IEEE Trans. on Electronic Devices, Vol.50, 2003. Then the process simulator Athena was used to realise the simulation structure of LDMOS which would be applied in the device simulator ATLAS. The profile of net doping was validated by the IMPACT calibrated simulation and Crystal-TRIM. Based on these calibration, I simulated the device characteristics for a set of n-LDMOS with an 8 nm-gate-oxide and the results show a good agreement with the measurements.

Further more, a same LDMOS with a 7 nm-gate-oxide was proposed and the challenge is the penetration of the charge in the channel due to the reduced gate oxide thickness. Light increase of the diffusion temperature does not play an important role since the thermal budget is limited by the CMOS part. An unusual tilt (60°) is bravely used in the LATID implantation and the channel condition is successfully adjusted. As a result, compared to the 8 nm-gate-oxide LDMOS, the breakdown voltage of this device (with 4 microns drift region longer) is increased by 15% meanwhile the resistance on is reduced 4%. This idea is employed by Philips ABCD-4 process.

It would be a great pleasure to get this award and contribute to a constructive researching atmosphere.

Thank you very much for considering my request.

Sincerely yours,